In two non-volatile memory cells (MC1, MC2) for memorizing complementary data, after the data therein is erased, the threshold voltage of both of the two non-volatile memory cells (MC1, MC2) will drop. However, it is assumed that the threshold voltage difference between the two non-volatile memory cells in a writing state before erasure of the data may remain after the data is erased. Therefore, even though the data is erased, the data written in before erasure may be read out again, leading to a security problem.
To solve this problem, conventionally, there is known such a technique that uniformizes the threshold voltage of each of the nonvolatile memory cells after they are erased.
For example, the erasing method disclosed in Japanese Patent Laying-Open No. 2001-307492 (PTD 1) determines whether all cell transistors in a sector have a threshold voltage higher than the lower limit in a first threshold voltage distribution corresponding to a programmed state. If the determination result is true, all cell transistors in the sector are erased simultaneously. Then, among the erased cell transistors, those cell transistors which have a threshold voltage lower than a detection voltage which is present between the upper limit of a second threshold voltage distribution corresponding to the erased state and the lower limit of the first threshold voltage distribution are detected. After the detected cell transistors are programmed individually, all cell transistors in the sector are erased simultaneously.